It has been a trend to increase the packaging density of wafers. The large integration of semiconductor ICs has been accomplished by a reduction in individual device size. With this reduction of device size, many challenges arise in the manufacture of the ICs.
Modern integrated circuits interconnect literally millions of devices to perform a certain function. The performance of the integrated circuits is related to the performance and reliability of the devices of which it is includes. Each device requires interconnections for exchanging electrical signals from one device to another device. Further, the trend of integrated circuits toward multi-level interconnections for present. Thus, there is a need of contact structures for providing electrically connecting paths for one level to another level.
Prior art for fabricating the interconnection includes forming a dielectric layer such as oxide over a semiconductor substrate for isolation. Then, a contact hole is formed in the dielectric layer by using conventional lithography techniques. In order to meet the requirement of the shrinkage of devices, the wide of the contact hole becomes smaller than ever. However, the aspect ratio of the contact hole in the integrated circuits is reduced due to the semiconductor devices have a higher integration. This is because the contact hole has a relatively narrowed wide and a relatively increased depth formed thereof. The conductive film can not be conformally formed on the surface of the contact holes. This results degrades the contact performance between conducting structures above and underlying the contact hole.
One propose to minimize the high aspect ratio issue is the use of a landing plug formed in the contact hole. Thus, the connecting structure is broken into two levels. Typically, the formation of the plugs is obtained by forming tungsten or doped polysilicon in the hole using a conventional manner. As known in the art, the integrated circuits include a cell area and a peripheral circuits area. However, the doped polysilicon plug with phosphorous dopants can only be applied in the NMOS area in the peripheral circuit area. Further, tungsten plug can not be used in the cell area because of the junction in cell area is formed by TiSi.sub.x and W/O gradient doping profile that is raised from the polysilicon layer. The junction leakage will be high which degrades the refresh time of the DRAM cell.